Research directions

SVP and Microgrids

Moore's law has over the last five decades provided exponential growth in chip densities at an unprecented doubling every 18-24 months. Over the last two decades this wealth of gates has been largely squandered by the industries reluctance to embrace explicit concurrency in microprocessor design to improve performance, relying instead on clock speed, which has resulted in excessive power dissipation and the so called memory wall. There are sound reasons for this direction, as concurrency is intrinsically difficult. The alternative of using hardware to extract and manage concurrency from a sequential instruction stream allows legacy code to drive each new generation of processor. The down side are control and storage structures that scale very badly and this scaling has eventually tolled the death knoll for this approach.

In CSA we are developing system virtualization techniques for scalable performance and power usage in future many-core chips. Along with the concept of microthreading we are exploring hardware support for concurrency management in order to provide complete solutions to the problems of the highly concurrent microprocessors we expect to see in the near future, i.e. 100s of processors in the next generation and perhaps 100,000 by 2020, by which time CMOS will be at its limit of scaling.

Projects: System Virtualization Platform, Microgrids, Microgrids (NWO), AETHER, Apple-CORE, ADVANCE

MultiProcessor System-on-Chip (MP-SoC) Design

Designers of MultiProcessor System-on-Chip (MP-SoC) based embedded systems are typically faced with conflicting design requirements regarding performance, flexibility, power consumption, and cost. As a result, MP-SoC-based embedded systems often have a heterogeneous system architecture, consisting of components that range from fully programmable processor cores to fully dedicated hardware blocks. Programmable processor technology is used for realizing flexibility, for example to support multiple applications and future extensions, while dedicated hardware is used to optimize designs in time-critical areas and for power and cost minimization.

The heterogeneity of modern embedded systems and the varying demands of their target applications greatly complicate the system design. It is widely agreed upon that traditional design methods fall short for the design of these systems as such methods cannot deal with the systems' complexity and flexibility. This has led to the notion of system-level design. System-level design methodologies typically urge designers to start with modeling and simulating (possible) system components and their interactions in the early design stages. Such system-level models usually represent application behavior, architecture characteristics, and the relation (e.g., mapping, hardware-software partitioning) between application(s) and architecture. These models do so at a high level of abstraction, thereby minimizing the modeling effort and optimizing simulation speed that is needed for targeting the early design stages. This high-level modeling allows for early verification of a design and can provide estimations on the performance, power consumption or cost of the design.

System-level design should be accompanied by a proper methodology for effective and efficient design space exploration. Due to the systems' complexity, it is imperative to have good (performance and power evaluation) tools for exploring a wide range of design choices, especially during the early design stages where the design space is at its largest. To this end, we are developing the Sesame (Simulation of Embedded System Architectures for Multi-level Exploration) framework which provides high-level modeling and simulation methods and tools for efficient system-level performance evaluation and exploration of heterogeneous MP-SoC-based embedded systems targeting the multimedia application domain. The Sesame methodology takes a designer systematically along the path from selecting candidate architectures, using analytical modeling and multi-objective optimization, to simulating these candidate architectures with our system-level simulation environment. This simulation environment subsequently allows for architectural exploration at different levels of abstraction (i.e., permits gradual refinement of the architecture performance models) while maintaining high-level and architecture independent application specifications.

Projects: Daedalus, EASY, VISUALISE, SCALOPES, MADNESS, CREED